Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■PCI-C bus bridge
Target PCI bus model
Explanation o PCI bus models have a PCI-C bus bridge device on the PCI bus to
bridge with the conventional C bus.
o Operations that are normally performed by I/O ports on models without a PCI
bus, such as memory-related operations, are often performed by manipulating
the PCI configuration register of the PCI-C bus bridge on models with a PCI bus.
o The PCI-C bus device performs subtractive decoding, and forwards bus cycles
that have not responded to within the PCI bus to the C bus.
u The implementation of the PCI-C bus bridge is thought to vary greatly
depending on the model. Compatibility of the PCI configuration register is not guaranteed.
For reference, here we show the results of an analysis of part of the PCI
configuration register of the PCI-C bus bridge of the PC-9821Xa, but the PCI
configuration register is set by the ITF and BIOS and should not be
manipulated by application programs. Since many settings are based on the
hardware, unnecessary operations may cause the system to become unstable.
Related I/O 0CF8h(BYTE),0CF9h(BYTE),0CFAh(BYTE),0CFBh(BYTE)
I/O 0CF8h(DWORD)
I/O 0CFCh
Vendor ID 1033h(NEC)
Device ID 0001h
Base class 06h(Bridge device)
Subclass 80h(PCI-Local bus bridge)
-------------------------------------------------------------------------------
PCI 40h
Name Unknown
Undocumented
Function
[READ/WRITE]
Bits 7-0: Unknown
* Set to 00h at initialization
Explanation o Details unknown
PCI 41h
Name Unknown
Undocumented
Function
[READ/WRITE]
Bits 7-0: Unknown
* Set to 10h at initialization
Explanation o Details unknown
PCI 42h
Name Unknown
Undocumented
Function
[READ/WRITE]
Bits 7-0: Unknown
* Set to 00h at initialization
Explanation o Details unknown
PCI 43h
Name Memory upper limit
Undocumented
Function
[READ/WRITE]
Bits 7-0: Unknown
Explanation o Sets the maximum memory address to be output to the local bus.
o Details unknown
PCI 44h
Name 16MB system space
Undocumented
Function
[READ/WRITE]
bit 7,6: Unknown
bit 5: 16MB system space usage
1 = Normal RAM
0 = Used as 16MB system space
bit 4-2: Unknown
bit 1: Write Enable For 00080000-0009FFFFh
bit 0: Read Enable For 00080000-0009FFFFh
11b = Read and write possible
10b = Write possible, read impossible
01b = Write impossible, read possible
00b = Read and write impossible
Explanation o Specifies whether the PCI-C bus bridge circuit responds to
access to the 16MB system space (00F00000-00FFFFFFh) or banks 8 and 9
(00080000-0009FFFFh). Related I/O 7FDBh bit 6 I/O 043Bh PCMC 59h bit 3-0 PCMC 78h
PCI 45-47h
Name Unknown
Undocumented
Function
[READ/WRITE]
bit 7: WE(WriteEnable)
1 = Write enabled
0 = Write disabled
bit 6: RE(ReadEnable)
1 = Read enabled
0 = Read disabled
bit 5,4: WE,RE
bit 3,2: WE,RE
bit 1,0: WE,RE
* Same as bit 7,6
----------------+-------+-------------------------------
Register | Bit | Memory range
----------------+-------+-------------------------------
45h | 1,0 | 0C0000-0C3FFFh (Extended ROM area)
45h | 3,2 | 0C4000-0C7FFFh (Extended ROM area)
45h | 5,4 | 0C8000-0CBFFFh (Extended ROM area)
45h | 7,6 | 0CC000-0CFFFFh (Extended ROM area)
46h | 1,0 | 0D0000-0D3FFFh (Extended ROM area)
46h | 3,2 | 0D4000-0D7FFFh (Extended ROM area)
46h | 5,4 | 0D8000-0DBFFFh (Extended ROM area)
46h | 7,6 | 0DC000-0DFFFFh (Extended ROM area)
47h | 1,0 | 0E0000-0E3FFFh (VRAM area)
47h | 3,2 | 0E4000-0E7FFFh (VRAM area)
47h | 5,4 | 0E8000-0EBFFFh (BIOS area)
47h | 7,6 | 0EC000-0EFFFFh (BIOS area)
----------------+-------+-------------------------------
The combinations set to 7,6 or 5,4 or 3,2 or 1,0 are as follows.
--------+-----------------------------------------------
Value | Operation
--------+-----------------------------------------------
11b | Read and write possible
10b | Write possible, read not possible
01b | Write not possible, read possible
00b | Read and write not possible
--------+-----------------------------------------------
Description o Sets the memory access behavior for the specific memory area set in each register.
PCI 48h
Name Unknown
Undocumented
Function
[READ/WRITE]
Bit 7-0: Unknown
* Set to 3Fh at initialization
Description o Details unknown
PCI 4Ch
Name Unknown
Undocumented
Function
[READ/WRITE]
Bit 7-2: Unknown
Bit 1: 8,9 bank separation
1 = Do not separate.
0 = Separate.
bit 0: Unknown
* Set to 3Eh at initialization
Explanation o Details unknown
PCI 4Eh
Name Unknown
Undocumented
Function
[READ/WRITE]
Bit 7-0: Unknown
* Set to 03h at initialization
Explanation o Details unknown
PCI 40h,44h,48h,4Ch
Name PCI-C BUS MEMORY REGION ADDRESS REGISTER
Undocumented
Target PC-9821Xa10, Xa9, Xa7, Xt13, Xa7e
Function
[READ/WRITE]
Bit 31-16: Memory Region Limit Address
Bit 15-0: Memory Region Base Address
* Registers the address of the memory area that the PCI-C bus bridge responds
to as an access from PCI to the C bus. Settings can be made in 64KB units.
* In the PC-9800 series, the following values are set for these registers.
---------+---------------+-----------------------------------
Register | Setting value | Memory range
---------+---------------+-----------------------------------
40h | 00EF0010h | 00100000-00EFFFFF
44h | FFFBFFFAh | FFFA0000-FFFBFFFF
48h | FFFEFFFEh | FFFE0000-FFFEFFFF
4Ch | 0000FFFFh | Disabled
---------+---------------+-----------------------------------
Explanation o Registers the address of the memory area that responds as an
access from PCI to the C bus.
PCI 50h,54h,58h,5Ch
Name PCI-C BUS MEMORY REGION ADDRESS REGISTER
Undocumented
Target PC-9821Xt, Xa, Xf
Function
[READ/WRITE]
bit 31-16: Memory Region Limit Address
bit 15-0: Memory Region Base Address
* Registers the address of the memory area that the PCI-C bus bridge responds
to as an access from PCI to the C bus. Settings can be made in 64KB units.
* In the PC-9800 series, the following values are set for these registers.
---------+---------------+-----------------------------------
Register | Setting value | Memory range
---------+---------------+-----------------------------------
50h | 00EF0010h | 00100000-00EFFFFF
54h | FFFBFFFAh | FFFA0000-FFFBFFFF
58h | FFFEFFFEh | FFFE0000-FFFEFFFF
5Ch | 0000FFFFh | Invalid
---------+---------------+-----------------------------------
Explanation o Registers the address of the memory area that responds as an
access from PCI to the C bus.
PCI 50-5Fh
Name Unknown
Undocumented
Target PC-9821Xa10, Xa9, Xa7, Xt13, Xa7e, Na7, Nx
Function
[READ/WRITE]
bit 7: Interrupt isolation
1 = Do not use interrupt
0 = Use interrupt
bit 6-4: Unused (always set to 000b)
bit 3-0: IRQ line
0000b = IRQ0
: :
1111b = IRQ15
* Sets the IRQ line used by each device.
---------+-----------------------------
Register | Device to be configured
---------+-----------------------------
50h | Timer
|
---------+----------------------------
51h | Keyboard
|
---------+----------------------------
52h | VSYNC
|
---------+----------------------------
53h | Unknown
|
---------+----------------------------
54h | Unknown
|
---------+----------------------------
55h | Secondary serial port
|
---------+----------------------------
56h | Unknown
|
---------+----------------------------
57h | Unknown
|
---------+----------------------------
58h | Unknown
|
---------+----------------------------
59h | IDE
|
---------+----------------------------
5Ah | FDC
|
---------+----------------------------
5Bh | FDC
|
---------+----------------------------
5Ch | Sound
|
---------+----------------------------
5Dh | Mouse
|
---------+----------------------------
5Eh | Unknown
|
---------+----------------------------
5Fh | Unknown
|
---------+----------------------------
Explanation o Defines the interrupt lines used by various motherboard devices.
o Normally, this setting is not changed.
PCI 60-63h
Name PIRQ ROUTE CONTROL REGISTERS
Undocumented
Function
[READ/WRITE]
bit 7: Routing of Interrupts
1 = Disabled
0 = Enabled
bit 6-0: IRQx# Routing Bits
000000b = IRQ0
: :
001111b = IRQ15
010000b =
: Reserved
111111b =
The interrupt signal lines set in each register and their corresponding slots are as follows.
---------+---------------------------+---------+---------+--------
Register | PCI interrupt signal line | Slot #0 | Slot #1 | Slot #2
---------+---------------------------+---------+---------+--------
60h | PIRQ0 | INTA | INTD | INTC
61h | PIRQ1 | INTB | INTA | INTD
62h | PIRQ2 | INTC | INTB | INTA
63h | PIRQ3 | INTD | INTC | INTB
---------+---------------------------+---------+---------+---------
Explanation o Sets which interrupt address of the interrupt controller on the
C bus the interrupt request signals PIRQ0-3 from the PCI bus are assigned to.
u In the PC-9800 series, the four channels of interrupt output from each PCI
board are wired to connect to a different signal line for each slot. This is
because multiple PCI boards with fixed interrupt output pins are used at the
same time.
Related I/O 0000h
I/O 0002h
I/O 0008h
I/O 000Ah
PCI 68h
Name Unknown
Undocumented
Target PC-9821Na7･Nx
Function
[READ/WRITE]
Bit 31-20: Unknown
Bit 19: Unknown
1 = Use sound function
0 = Do not use sound function
Bit 18-0: Unknown
Explanation o Details unknown
Related I/O 881Eh Bit 5
-------------------------------------------------------------------------------
===============================================================================
■PCI-Local Bus Bridge
Vendor ID 1033h (NEC)
Device ID 0002h
Base Class 06h (Bridge Device)
Subclass 80h (PCI-Local Bus Bridge)
-------------------------------------------------------------------------------
PCI 40h
Name 16MB system space
Undocumented
Function
[READ/WRITE]
Bit 7-2: Unused
Bit 1: 16MB system space usage
1 = Normal RAM
0 = Used as 16MB system space
Bit 0: Unused
Explanation o Registers the usage of the 16MB system space to the local bus bridge circuit.
o Details unknown
Related I/O 043Bh
PCMC 78h
PCI 44h
Name Unknown
Undocumented
Function
[READ/WRITE]
Bit 7-1: Unused
Bit 0: Unknown
Explanation o Details unknown
Related
-------------------------------------------------------------------------------